What both AMD and TSMC are doing is very impressive, maybe not at the level of Intel with Foveros (for the moment) but what is certain is that although technologically they are not at the same level for now, in performance they are going to be leaders (unless there is a surprise with Alder Lake-S).

AMD Zen 3 3D Cache, a 15% jump in gaming performance

The numbers slipped by Lisa Su give as an average result that figure, but now we know the curiosities of the whys and wherefores. Adding one more vertical chip as an increased cache will not be, as speculated, a level 4 cache, or in other words, it won’t be the typical Victim Cache technically speaking.

It’s all quite simpler from the theory, but from the practice the numbers are overwhelming and we’ll explain ourselves.

What AMD achieves with this vertical cache is that Windows and CCDs see the added chip as “transparent”, i.e. there is no physical change for software or hardware in the way it works between cores and the IOD.

What you will see will be one more L3 cache block, which will be manufactured at 7nm by TSMC and will measure a whopping 6 x 6mm (36mm2) connected directly to the CCD caches via TSV. And here comes the magic, because in the case of the 5950X that was shown at the time with this technology we are talking about nothing less than 192 MB of L3 in total for the existing 64 of the original model that we can buy today.

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Dizzying TSV figures, at Intel’s level


Each CPU will have more than 2 TB/s of bandwidth thanks to this new cache and its TSV connections, which we now know are made by Bumps in what is called “Face Down”, Each TSV is connected from the FEOL of each CCD to the Bonding Surface by copper Nails. These are in direct contact with the BEOL of this new cache, which allows the exchange of information from the substrates and caches.

To give us an idea of the complexity of all this vertical stacking, it is estimated that for each 4 MB L3 partition on a CCD there are 3000 TSVs with a size ranging from 6.1 μm to 17.3 μm thick.


To square the circle more stratospheric data is given, as 56 TSVs are calculated in the SMU and 14 more in the so-called test area.

What do we have in total in the new 5950X? Well, a whopping 24070 TSVs to connect both substrates, where as we said before the area of the new AMD 3D Cache is only 36 mm2. Undoubtedly overwhelming figures that will allow AMD to beat Intel to the ground, at least momentarily.